Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
A flash memory is a type of memory that can be erased and reprogrammed in blocks instead of one byte at a time. A typical flash memory comprises a memory array, which includes a large number of memory cells. Changes in threshold voltage of the memory cells, through programming of charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed, such as by charging the charge storage structure. The data in a cell of this type is determined by the presence or absence of the charge in the charge storage structure. The charge can be removed from the charge storage structure by an erase operation.
Each memory cell can be programmed, for example, as a single bit cell (i.e., single level cell—SLC) or a multiple bit cell (i.e., multilevel cell—MLC). Each cell's threshold voltage (Vt) is representative of the data that is stored in the cell. For example, in a single bit cell, a Vt of 1.5V can indicate a programmed cell while a Vt of −0.5V might indicate an erased cell.
A multilevel cell has multiple Vt ranges that each represents a different state. Multilevel cells can take advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific Vt range for the cell. This technology permits the storage of data values representing n bits (e.g., two or more bits) per cell, depending on the quantity of Vt ranges assigned to the cell.
As the size of memory cells has decreased in order to increase the density of memory devices, the resulting proximity of the memory cells can cause problems with capacitive coupling. For example, floating gate-to-floating gate capacitive coupling between adjacent memory cells can cause the programming of one memory cell to “pull-up” an already programmed memory cell to a higher threshold voltage. This coupling can result in errors reading the affected memory cell since its threshold voltage can be increased beyond a normal read voltage for a particular programmed state.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art to reduce the effects of, for example, charge storage structure to charge storage structure coupling.